Preprint: Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices
A preprint evaluates differentiable logic gate networks (Diff-Logic), compiled into pure boolean circuits, as a low-latency EEG classification option for resource-constrained BCIs. Across four EEG datasets and two task types — binary dementia screening and three-class emotion recognition — Diff-Logic reached 80.2% Macro F1 on dementia screening, 6.8 points above the multilayer perceptron baseline, and on power-constrained devices the MLP ran 2.3× slower and occupied 14× more memory, while Diff-Logic's inference time stayed nearly flat as model size grew 10×. The study has not been peer reviewed.