The researchers report that Diff-Logic achieved 80.2% Macro F1 on dementia screening, outperforming the MLP baseline by 6.8%; on a power-constrained device the MLP incurred 2.3x higher latency and 14x larger model size, while Diff-Logic inference time stayed nearly constant across a 10x model scale increase with a peak 2.9x speedup over MLPs. This study is a preprint and has not been peer reviewed.
Preprint: Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices
Summary
A preprint evaluates differentiable logic gate networks (Diff-Logic), compiled into pure boolean circuits, as a low-latency EEG classification option for resource-constrained BCIs. Across four EEG datasets and two task types — binary dementia screening and three-class emotion recognition — Diff-Logic reached 80.2% Macro F1 on dementia screening, 6.8 points above the multilayer perceptron baseline, and on power-constrained devices the MLP ran 2.3× slower and occupied 14× more memory, while Diff-Logic's inference time stayed nearly flat as model size grew 10×. The study has not been peer reviewed.
Why it matters
The edge angle is what matters: compiling the model into boolean circuits keeps latency and footprint nearly flat as it scales, which is precisely the constraint that keeps standard neural decoders off power-limited wearable and implantable hardware.
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arxiv.org 2026-07-20